The present invention relates to a logic circuit and specifically to a circuit construction technique for reducing delay and power consumption of a sequential circuit.
Among the presently-existing semiconductor integrated circuits, static circuits, typified by CMOS (Complementary Metal Oxide Semiconductor) circuits, have been widely used. The CMOS circuits have an advantage such that the output does not change so long as the input does not change, and the current consumption includes only a small leak component and an active component which occurs at a value transition, resulting in a relatively small current consumption. On the other hand, a disadvantage of the CMOS circuits is a relatively-large energy delay product in a high speed operation.
FIG. 62 conceptually shows a CMOS circuit. In general, the CMOS circuit includes a circuit for realizing a logical operation of a function to be realized, i.e., evaluation function f, and a circuit for realizing a logical operation of a complementary function of evaluation function f, i.e., function f*. Function f and function f* are generally realized by an N-type transistor and a P-type transistor, respectively. Signals generated by the functions are propagated to the functions at subsequent steps, whereby a circuit operation is realized. In the CMOS circuit, two circuits are constructed for one function, and therefore, the circuit scale and the input load of signals are relatively large. Especially, the P-type transistor needs to have a transistor size about twice as large as that of the N-type transistor in view of the difference in carrier mobility, and therefore, the increase in input load is remarkable. This problem is common among the static circuits, including DCVSL (Differential Cascode Voltage Switch Logic), as well as the CMOS circuits.
A known circuit structure which compensates for the disadvantages of the static circuit is a dynamic circuit (see, for example, the specification of U.S. Pat. No. 5,532,625 (FIG. 3A)). FIG. 63 conceptually shows a dynamic circuit. In general, the dynamic circuit performs a time-sharing operation of an initialization phase for output with initialization function g and an evaluation phase for input with a function to be realized, i.e., evaluation function f. The operation with evaluation function f and the operation with initialization function g are referred to as “evaluation operation” and “precharge operation”, respectively. Through the evaluation operation, a signal is generated and propagated, and the function at the subsequent stage performs a precharge operation and an evaluation operation, whereby a circuit operation is realized. Thus, in the dynamic circuit, it is only necessary to add an initialization function to one function, and therefore, the circuit scale and the input load of signal are relatively small. Especially, the initialization operation is performed using a clock, and therefore, the input load depends only on evaluation function f and is about a ⅓ of that of the CMOS circuit.
However, there is a problem that, since the initialization phase and the evaluation phase alternately occur all the time in the dynamic circuit, the activation yield is higher than in the static circuit. Thus, it is necessary to reduce the activation yield by, for example, introducing clock gating control. In the dynamic circuit, a clock is used for an operation of a combinational circuit, and therefore, design restrictions as to the clock tree structure, clock waveform adjustment, etc., become complicated, and the design difficulty increases. Known techniques for reducing the activation yield of the dynamic circuit include a technique which uses an asynchronous circuit (see, for example, Scott Hauck, “Asynchronous Design Methodologies: An Overview”, Proceedings of IEEE, Vol. 83, No. 1, January, 1995, pp. 69-93 (FIGS. 7 and 8)) and a technique which performs clock control according to a variation of the input signal (see, for example, Japanese Laid-Open Patent Publication No. 5-206791 (FIG. 1)).
However, in the asynchronous circuit, in general, the operation is completed by a handshake of a request signal and a response signal, and therefore, a circuit for the handshake is necessary. Since an operation of the combinational circuit is accompanied by a handshake, the design difficulty is extremely high. On the other hand, applications of clock control performed according to a variation of the input signal are limited to sequential elements, such as flip flops, memories, and the like, in view of the principle of detecting a variation of the input signal.
Thus, it is difficult to achieve both higher speed operation and lower power consumption in a logic circuit because of the increase of the input load in the static circuit, the increase of the activation yield and extremely-high design difficulty in the dynamic circuit, generation of an overhead of a handshake circuit and extremely-high design difficulty in the asynchronous circuit, and application restrictions in the clock control performed according to a variation of the input signal. It is difficult to solve the problems about the signal load, activation yield, circuit scale, etc., at the same time so long as the circuit operation is based on any one of a rule that a result of sequential function evaluation of a signal input is propagated as in the static circuit and a rule that a result of periodic function evaluation of a signal input is propagated as in the dynamic circuit.